1. Field of the Invention
The present invention relates to a graphic accelerator for performing a high-speed image display.
2. Description of the Background Art
With reference to FIG. 16, image information which has been processed in a conventional two dimensional graphic accelerator will be described. In FIG. 16, RGB (x,y) represents R color information, G color information, and B color information at a pixel location (x, y).
The conventional graphic accelerator thus processes R/G/B color information of a few bit each for each of pixels which are basic units constituting a screen to be displayed. R/G/B color information of each unit pixel are temporarily stored in an external image memory region, read out therefrom and processed as data.
In a 3D graphic accelerator (3D: three dimension) employing Z buffering method, information to be processed includes depth information (Z value) and transparency information (xcex1 value) given for each pixel, texture which is pattern data to be pasted on to a polygon and so on in addition to R/G/B color information. Similarly, the information is temporarily stored in an external image memory region, read out therefrom and processed as data.
The size of a screen (the number of pixels) has been increasing recently and the required image memory capacity has also further increased.
In the conventional graphic accelerator, however, when the amount of data to be stored in the image memory increases, the amount of data to be transferred between the graphic accelerator and the image memory increases causing a undesirable effect on the process speed. Particularly in the graphic accelerator capable of processing three dimensional image, as the required image data memory capacity is large and data to be processed is considerable, the improvement in image-forming process performance is hard to achieve.
For the achievement of high-speed processing, the graphic accelerator and the image memory are required to be incorporated in one chip formed on the same semiconductor substrate. The increase in image memory capacity hampers such requirement.
Hence, the present invention provides a graphic accelerator capable of processing image data at high speed by suppressing the increase in image memory capacity.
A graphic accelerator according to one aspect of the present invention generates display data based on data stored in an image memory and includes; a storage control unit receiving a plurality of pixels each having three types of color information such as RGB, deleting one of three types of color information in each pixel, and storing color information of the plurality of pixels in the image memory such that the color information includes a pixel having two types of color information except first type color information among three types of color information and a pixel having two types of color information except second type color information different from the first type color information among three types of color information; and an interpolation process unit interpolating color information deleted by the storage control unit with a pixel including deleted color information among the plurality of pixels stored in the image memory, for each of the plurality of pixels stored in the image memory. The graphic accelerator supplies display data as an output according to the plurality of pixels stored in the image memory and interpolation result of the interpolation process unit.
According to the graphic accelerator described above, one type of color information among three types of color information is deleted and two types of color information are stored in the image memory for each pixel. Then, deleted color information is interpolated with a pixel which is stored in the image memory and includes deleted color information. Thus, even with a larger screen, information to be stored in the image memory can be reduced. As a result, the amount of data to be transferred between the image memory and the graphic accelerator can be reduced. Hence, more rapid image processing can be achieved. In addition, as the image memory capacity can be decreased, the image memory and the graphic accelerator can be incorporated in a single chip.
Preferably, the storage control unit stores two types of color information except the first type color information among the three types of color information in the image memory for each of the plurality of pixels arranged in a direction of even scan lines, and stores two types of color information except the second type color information among the three types of color information in the image memory for each of the plurality of pixels arranged in a direction of odd scan lines.
According to the above described graphic accelerator, capacity of image memory can be reduced to two-thirds of the capacity of conventional device. In addition, as the process is performed in the direction of scan line, the interpolation process can be readily embodied in a hardware and a compact circuit structure can be achieved.
Preferably, the storage control unit stores two types of color information except the first type color information among the three types of color information in the image memory for each of a first plurality of pixels arranged as a matrix and included in the plurality of pixels, and stores two types of color information except the second type color information among the three types of color information in the image memory for each of a remaining second plurality of pixels included in the plurality of pixels.
According to the above-described graphic accelerator, image memory capacity can be reduced to two-thirds of the capacity of conventional device.
Preferably, the storage control unit divides the plurality of pixels into a plurality of blocks, deletes color information so that the plurality of blocks each include a first type pixel not having the first type color information of the three types of color information and a second type pixel not having the second type color information of the three types of color information, and the interpolation process unit interpolates the deleted color information of a pixel to be interpolated with a pixel having the deleted color information and included in the same block as the pixel to be interpolated.
According to the above-described graphic accelerator, the plurality of pixels are divided into blocks and one of three types of color information is deleted for one pixel and another of three types of color information is deleted for another pixel in each block and the resulting color information is stored in the image memory. Interpolation is performed block-wise. Thus, the image memory capacity can be reduced to two-thirds of the capacity of conventional device.
Preferably, the storage control unit deletes color information such that the plurality of pixels to be output include a first type pixel not having B color information among the three types of color information, a second type pixel not having R color information among the three types of color information, and a third type pixel not having G color information among the three types of color information.
According to the above-described graphic accelerator, R color information is deleted for one pixel, G color information is deleted for another pixel, and B color information is deleted for still another pixel. Thus, image memory capacity can be reduced to two-thirds of the capacity of the conventional device.
Preferably, each of the plurality of pixels written into the image memory includes the same color information. Particularly, each of the plurality of pixels written into the image memory includes G color information.
According to the above-described graphic accelerator, display result similar to an original image can be obtained when G color information is not deleted.
Particularly, the plurality of pixels are arranged in the image memory such that a first line in which all pixels arranged in the scan direction of the screen are the first type pixels, a second line which is next to the first line and in which all pixels arranged in the scan direction of the screen are the second type pixels, and a third line which is next to the second line and in which all pixels arranged in the scan direction of the screen are the third type pixels are repeatedly arranged.
According to the above-described graphic accelerator, first color information is deleted from three types of color information with regard to pixels in (3N+1)th scan lines, second color information is deleted from three types of color information with regard to pixels in (3N+2)th scan lines, and third color information is deleted from three types of color information with regard to (3N+3)th scan lines. Thus, the image memory capacity can be reduced to two-thirds of the conventional device capacity. In addition, as process is performed in the direction of scan line, interpolation process can be readily embodied in a hardware and a compact circuit structure can be obtained.
A graphic accelerator according to another aspect of the present invention generates display data based on data stored in an image memory and includes; a storage control unit receiving a plurality of pixels each having color information and Z value information designating depth, dividing the plurality of pixels into a plurality of blocks, updating shared Z value information and storing the resulting information in the image memory on each block basis, comparing Z value information of a pixel and shared Z value information stored in the image memory on each block basis, and updating color information of the pixel and storing the resulting information in the image memory according to a hidden surface removal process, and a circuit supplying the display data as an output employing the plurality of pixels stored in the image memory.
Preferably, each of the plurality of pixels to be supplied as an input further includes xcex1 value information designating transparency. The storage control unit updates shared xcex10 value information and stores the resulting information in the image memory on each block basis, compares Z value information of the pixel and shared Z value information stored in the image memory, updates color information of the pixel according to the hidden surface removal process and an alpha blending process based on the shared xcex1 value stored in the image memory and stores the resulting information in the image memory.
Particularly, the image memory includes a Z buffer storing Z value information shared on each block basis and a frame buffer storing color information of each of the plurality of pixels and xcex1 value information shared on each block basis.
According to the above-described graphic accelerator, the plurality of pixels are divided into blocks and each depth information Z and transparency information xcex1 are shared by pixels in each block. Thus, the image memory capacity of the Z buffer and the frame buffer can be significantly reduced compared with a conventional approach where depth information Z and transparency information xcex1 are stored for every pixel. Hence, more rapid image processing can be achieved. In addition, as the reduction of image memory capacity is allowed, the image memory and the graphic accelerator can be incorporated in a single chip.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.